A Robust Strategy for Total Ionizing Dose Testing of Field Programmable Gate Arrays

We present a novel method of FPGA TID testing that measures propagation delay between flip-flops operating at maximum speed. Measurement is performed on-chip at-speed and provides a key design metric when building system-critical synchronous designs. Corresponding (and Presenting) Author: Edward Wilcox is with MEI Technologies Inc., c/o NASA GSFC, Code 561.4, Greenbelt, MD 20770 (USA) , Email: ted.wilcox@nasa.gov Contributing Authors: Melanie Berg (melanie.d.berg@nasa.gov), Mark Friendlich (mark.r.friendlich@nasa.gov), Joseph Lakeman (joseph.p.lakeman@nasa.gov), and Hak Kim (hak.s.kim@nasa.gov) are with MEI Technologies Inc., c/o NASA GSFC, Code 561.4, Greenbelt, MD 20770 (USA). Ken Label (kenneth.a.label@nasa.gov) and Jonathan Pellish (jonathan.a.pellish@nasa.gov) are with NASA Goddard Space Flight Center, Code 561.4, Greenbelt, MD 20770 (USA). Session Preference: Hardness Assurance Presentation Preference: Oral