200M-4Gbps wide-range clock and data recovery circuit

A design of dual loop wide-range clock data recovery circuit for multi-channel transmitter-receiver is proposed. This paper presents a delay line to prevent the increase of jitter in recovered data when the input data is wide-range, which is used greatly in multichannel transmitter-receivers. Proposed Clock and Data Recovery Circuit (CDR) frequency is 200Mbps-4Gbps, the delay steps in the proposed delay line is 7ps-12ps. Designed CDR is tested with 0.18µm CMOS process.