Studies of fabrication process for logic gate array using Pb‐alloy josephson junction

Using a Pb-alloy Josephson integration process with basic rules of junction dimension 3.5 μmϕ, minimum line width 2.5 μm, and junction current density Jc = 500 A/cm2, a Josephson logic gate array with integration of 576 gates/chip has been fabricated. For the device fabricated in the Pb-In-Au/oxide/Pb-Bi system, hillocks have been observed in the base electrode film, and voids frequently occur in the counter-electrode film, with the junction being short. This failure has been attributed to the electromigration of Bi in the counter electrode into the base electrode, thereby breaking the junction. Using a Pb-In-Au film formed at low temperature (∼0°C) for a base electrode and a Pb-Au film for a counter electrode, junction shorts have been eliminated completely. A junction current variation of ±10% has been obtained which is one-half that for conventional junctions. The yield for good chips by visual inspection is 10 30 percent. The delay time of signal propagation has been measured by the operation of various gate chain circuits using fabricated logic array chips. The gate delay time of 33 ps for the 2-input OR gate and 54 ps for the 2-input AND gate has been obtained.