Hardware-software co-design architecture for joint photo expert graphic XR encoder

In recent years, because of to the fast growing of internet and digital multi-media, new image compression algorithms are needed to reduce the transferring bandwidth and the decay of image quality. Joint Photo Expert Graphic (JPEG) extended range (XR) is a new standard for still image compression. Compared to previous standards, it provides better image quality and plentiful pixel format. However, the better image quality often comes with the higher computation complexity. In this study, the authors propose a hardware–software co-design architecture for JPEG XR encoder. For photo overlap transform (POT), and photo core transform (PCT), the complicated parts of JPEG XR, the authors propose new algorithms which eliminate data dependency in the basic filters of POT and PCT so that operations can be executed in parallel. The processing rate of the new algorithms is much faster. The authors also demonstrate a basic filter with multiple functions, which can be time-shared by POT and PCT; the hardware cost can be therefore reduced. Moreover, a memory saving scheme is proposed. Therefore the proposed architecture is suitable for stand-alone application-specific integrated circuit (ASIC). In our co-design, POT and PCT are implemented in hardware and then mapped to field programmable gate array (FPGA), whereas the other procedures of JPEG XR such as quantisation are executed by ARM926-EJ processor. The overall performance of our hardware architecture is 50 fps for 4:4:4 HDTV format at 166 MHz.