Gate and Bulk-Driven Four-Quadrant CMOS Analog Multiplier

This work presents and validates the design of a four-quadrant analog multiplier based on the bulk-driven technique. Using the source–gate as well as the bulk–source voltages of a PMOS transistor as input ports, the multiplication task can be achieved. The AC signals are injected into the bulk terminals by means of a very-low-frequency programmable high-pass RC network which also serves to set its proper DC operation point. Although two RC networks are required, this multiplication cell is composed of only seven PMOS transistors and two coupling capacitors which makes it a very compact circuit. Furthermore, no preprocessed signals like the sum of \(\pm \,v_x \pm \,v_y\) are required at the input ports. The implemented circuit shows a bandwidth of 50 MHz for an output capacitance of 40 pF and a THD lower than 1\(\%\) for gate/bulk input amplitudes below 0.2 Vp. The power consumption of the multiplication core is 660 \(\upmu \)W and 2.6 mW including output buffers. In order to simulate and fabricate this circuit, an ON Semi 0.50 \(\upmu \)m CMOS standard technology is used, showing a silicon area consumption of \(280\,\upmu \hbox {m} \times 400\,\upmu \)m including output buffers. The proposed multiplier is suitable for biomedical, AM modulation, base-band modulation and analog computation.