Use of stablilizing ramp to eliminate limit cycle in converters with power semiconductor filter

“Power Semiconductor Filter (PSF)” utilizes power semiconductor devices to eliminate the input current harmonics of switched-mode power converters. The concept is based on using a series pass device (SPD), which acts as a controllable current source, to program the input current waveform of the converter. The quiescent point of the SPD is stabilized at the boundary between the linear and saturation region by regulating the voltage across the SPD near its saturation voltage. Thus, the power loss of the SPD is minimized. Experiments reveal that the overall efficiency is found to be comparable with the conventional passive-type filter. This paper will firstly discuss possible occurrence of limit cycles under peak-voltage control to regulate the voltage across the SPD, and will then examine the use of a stabilizing ramp in the pulsewidth modulator to tackle such phenomenon. The effectiveness of the introduced stabilizing ramp will be exemplified experimentally on a 48W, 40–140V/24V buck converter. Small-signal modeling, design, and analysis of the entire system will be presented.