An improvement of router throughput for on-chip networks using on-the-fly virtual channel allocation

With the trend to integrate a large number of cores on a single chip, Network-on-Chips (NoCs) are becoming more important for communication on System-on-Chips (SoCs). Designing high throughput and low latency on-chip networks with reasonable area overhead is one of the main technical challenges. This paper proposes an architecture of router with on-the-fly virtual channel (VC) allocation for high performance on-chip networks. By performing the VC allocation during the time a packet is traversing the crossbar switch, the pipeline of a packet transfer can be shortened in a non-speculative fashion without the penalty of area. The proposed architecture has been implemented on FPGA and evaluated in terms of network latency, throughput and area overhead. The experimental results show that, the proposed router with on-the-fly VC allocation can reduce the network latency by 40.9%, and improve throughput by 47.6% as compared to the conventional VC router. In comparison with the look-ahead speculative router, it improves the throughput by 8.8% with 16.7% reduction of area for control logic.