Logic gate structure and its manufacture

PURPOSE: To change a logic function to execute the selected one of two or more logic functions. CONSTITUTION: A plurality of FETs Q0 A to Qn-1 A and Q0 B to Qn-1 B are arranged in a structure 10 to ordinarily execute a first logic function like a NAND. The structure 10 is converted by selectively implanting ion to at least one channel area of the FET with enough ion of a specified kind so that a fixed logic state (constantly ON or OFF) is held to all logic values of applied gate voltage to execute a second logic function like a NOR. Separately, one of the logic states is set as a 'stack high' (constant logic high output) or a 'stack low' (constant logic low output). Ion implantation to the channel is substantially impossible to be detected and the structure 10 is capable of being set as high resistance to reverse engineering.