Hardware implementation of a high speed self-synchronizing cipher mode

Pipelined statistical cipher feedback (PSCFB) mode is a new mode of operation for block cipher encryption. It is an improved version of conventional SCFB mode with higher throughput. SCFB mode has the mechanism of self synchronization to recover from bit slips during transmission in a communication channel. The mechanism of SCFB mode resembles output feedback (OFB) mode and cipher feedback (CFB) mode. However it has self synchronization that OFB mode does not and has higher efficiency than CFB mode. To improve the throughput, PSCFB is a modified version of SCFB that allows for the pipelining of the underlying block cipher while still preserving the efficiency and self-synchronizing capabilities. In this paper, the Advanced Encryption Standard (AES) with a pipeline architecture is used as the block cipher in PSCFB. The PSCFB system is designed, simulated and synthesized targeted to an Altera Cyclone IV FPGA. The structures and processes of both the encryption and decryption are presented. The system performance is analyzed based on the simulation and synthesis results.