Design and Optimization of 1- Bit Magnitude Comparator Using Adiabatic Logic

This paper proposed a 1- bit magnitude comparator design using DC-DB PFAL (direct current diodes founded positive response adiabatic logics) technique. The main motivation of this paper is to provide a way to reduce the any digital circuit’s power dissipations, as power dissipation is the one of the primary importance of digital circuits. This paper contains the design and simulation of comparator circuit which is simulated in cadence virtuoso tool at 180nm technology node. The designed 1-bit magnitude comparator circuit design using DC-DB PFAL comparator is compared with the ECRL magnitude comparator 94% and MPFAL comparator is 82%, whereas a PFAL comparator is … power consumption is more efficient than the ECRL comparator. The finding show that the PDP for the proposed design is greatly improved as likened to current conventional designs.