A CMOS VLSI chip for filtering of TV pictures in two dimensions

Low-cost digital transmission of color TV signals over the channels of a future broad-band network (Integrated Services Digital Network, or ISDN) requires data reduction by digital low-pass filters. Low-pass filtering of a TV picture amounts to process pixels which are adjacent in either the horizontal or vertical direction. For this purpose, the pixels must be stored in a delay unit. A VLSI chip with a delay unit is reported that is based on a resettable first-in-first-out (FIFO) memory and a pipelined arithmetic unit. The FIFO concept starts from a three-transistor cell array which is accessed by a pointer and customized to a FIFO memory by suitable second-layer metal wiring. Rather than cascade registers, the FIFO memory can be adapted to different standards by the reset signal for the pointer. The approach results in a regular compact design (80-kbit transistors, 31 mm/SUP 2/). An experimental chip fabricated with 1.5-/spl mu/m CMOS technology operates up to 22 MHz (typical values). A data stream of 22/spl times/32 Mb/s is exchanged between the memory and the arithmetic basic unit.