A Simulation Study on the Effects of Interface Charges and Geometry on Vertical GAA GaN Nanowire MOSFET for Low-Power Application

The effects of interface charges on the performances of gate-all-around (GAA) GaN vertical nanowire MOSFETs with different geometries have been studied. Geometrical effect on the gate current of vertical GAA GaN nanowire MOSFET has also been analysed for the first time. In the ideal condition, the circular geometry nanowire (CGN) MOSFET exhibits the best performance with subthreshold swing (SS) of 62 mV/dec, drain-induced barrier lowering (DIBL) of 14 mV/V, and ON/OFF current ratio ( $I_{ON}/I_{OFF}$ ) of ~108. The triangular or hexagonal geometry nanowire (TGN or HGN) MOSFET suffer from large gate leakage current due to the field enhancement at sidewall corners. It is also known that interface traps at the sidewall surface of vertical nanowires deteriorate the overall device performance. The HGN MOSFET with m-plane sidewall demonstrates the best performance with SS of 69 mV/dec and DIBL of 13 mV/V, while the TGN MOSFET with a-plane sidewall exhibits the worst performance with SS of 112 mV/dec and DIBL of 101 mV/V.