Evaluation of Inverse Lithography Technology for 55nm-node memory device

ABSTRACT Model based OPC has been generally used to correct prox imity effects down to ~50 nm critical dimensions at k 1 values around 0.3. As design rules shrink and k 1 drops below 0.3, however; it is very hard to obtain enough process window and acceptable MEEF (Mask Er ror Enhancement Factor) with conven tional model based OPC. Recently, ILT (Inverse Lithography Technology) has been introduced and has demonstrated wider process windows than conventional OPC. The ILT developed by Luminescent uses level-set methods to find the optimal photo mask layout, which maximizes the process window subject to mask manufacturing constraints. We have evaluated performance of ILT for critical dimensions of 55nm, printed under conditions corresponding to k 1 ~ 0.28. Results indicated a larger process window and better pattern fidelity than obtained with other methods. In this paper, we present the optimization procedures, model calibration and evaluation results for 55 nm metal and contact layers and discuss the possibilities and the limitations of this new technology. Key words : Inverse Lithography Technology, Process wi ndow, Model calibration, OPC, RET, MEEF