Low Leakage III-V/Ge CMOS FinFET Design for High-Performance Logic Applications with High-k Spacer Technology

We propose a novel optimized design strategy by considering the correlated effects of $high-{\kappa}$ gate oxide and spacer dielectric on GIDL and DIBL for high performance nanoscale CMOS with III-V/Ge channel tri-gate FinFET structure. By investigating the transition of GIDL mechanism from vertic...