Low-Power Hardware Architecture for Depthwise Separable Convolution Unit Design

Depthwise separable convolution is useful for building small and lightweight networks. However, the hardware design of depthwise separable convolution unit has not been well studied. With an analysis, we find that many multiplications in depthwise separable convolution can be omitted. Based on this observation, in this paper, we present a novel hardware design to avoid unnecessary multiplications (by using the clock gating technique) for power saving. Experiments on MobileNetV1 model show that the proposed hardware unit can greatly reduce power consumption.