LAYOUT DESIGN SIMULATION OF AREA AND POWER EFFICIENT 10 TG FULL SUBTRACTOR

Full Subtractor is an essential component in designing various hardware circuits and variety of processors. Combinational logic has extensive applications in computing low power VLSI design. In the world of technology, it has become necessary to develop various new design methodologies with reduction in power consumption, area and number of transistors. In this paper, Full Subtractor has designed using 10-transistors on 32nm CMOS technologies. Three different layout design techniques has been used in this paper i.e.; auto generated, semi custom and fully custom layout design and comparison is done in terms of power and area. The fully custom full subtractor layout design has shown the improvement of 30.41%/74.21% in power dissipation and 13.19%/69.01% in area.