Dual-Interlocked Logic for Single-Event Transient Mitigation

A combinational logic family, termed dual-interlocked logic (DIL), designed for single-event transient (SET) mitigation has been fabricated at a 16nm/14nm bulk FinFET technology generation and irradiated with heavy ions. Through both simulation and heavy-ion irradiation, DIL is shown to be robust to both single- and dual-node strikes. Results are compared to cascode voltage switch and standard logic to show the effectiveness of the logic family in mitigating SETs at the gate level. Three exemplar radiation-hardened-by-design synchronous systems using DIL, spatial triple modular redundancy (TMR), and temporal TMR are compared across area, power, delay, and hardness relative to an unhardened baseline system. The system utilizing DIL exhibits desirable tradeoffs compared to spatial and temporal TMRs.