Voids Inspection Capability Study in First-Level Interconnects for Flip Chip Packages

The evolution of electronic packaging to enable 3D heterogeneous integration has led to a continuous downscaling of solder interconnects. With the emergence of packaging technologies such as silicon bridges, interposers and die-to-die stacking, micro bumps in electronic packages are getting smaller and smaller. The shrinkage of bump size to cater for higher I/Os in increasingly complex packaging design can lead to weaker interconnect joints. Common defects that have plagued bigger solder joints could become critical in smaller micro bumps. One such defect is voiding. The presence of voids in small micro bumps not only reduces solder volume and affects joint structural integrity but also restricts current flow and increases current density in the joint. This paper presents the study of void formation in first-level interconnects and the inspection capability of void detection.