Low power sigma delta decimation filter

This paper presents an efficient design and implementation of a low power sigma delta digital decimation filter. We implement a low power decimation filter with a narrow transition finite impulse response (FIR) filter using a canonic signed digit number (CSD) system. We use multi-stage multi-rate signal processing to design and implement half-band filters and narrow transition band FIR filters. The decimation filter is designed using Simulink, DSP Blockset and simulated using Matlab. The FIR filter has been coded in Verilog and implemented using FPGA Xilinx 4000 technology. The power consumption of the proposed decimation filter is reduced by 67% compared to the conventional 4-stage comb-FIR architecture.