Integration of high-performance, low-leakage and mixed signal features into a 100 nm CMOS technology

Low voltage operation in sub-0.25 /spl mu/m requirements mean that the simultaneous integration of all components on a single chip - high performance, low leakage and mixed-signal components - is crucial. In this paper, we present the successful integration of a low leakage gate-dielectric using a triple-gate-oxide process with 16 /spl Aring//24 /spl Aring//52 /spl Aring/ layers, a low-k BEOL and mixed signal components. The 1.5 V SRAM cell with a footprint of 1.26 /spl mu/m/sup 2/ is the smallest 1.5 V cell reported.