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A Staggered for NAND DRAM array architecture a Gbit scale integration
A Staggered for NAND DRAM array architecture a Gbit scale integration
1994
Shinichiro Shiratake
Hiroaki Nakano
Yukihito Oowaki
Shigeyoshi Watanabe
Kazunori Ohuchi
Komukai Toshiba-clio
Nand Dram
Keywords:
NAND gate
Gigabit
Electronic engineering
Architecture
Dram
Computer science
Embedded system
Computer hardware
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