DYN1: a 66 MHz front end analog memory chip with first level trigger capture for use in future high luminosity particle physics experiments

Abstract DYN1 is a 32 channel, 128 cell analog memory with continuous write and read access. The chip amplifies the detector signals and integrates the signal currents onto capacitors within the memory during each bunch crossing interval. Dense dynamic logic circuitry accepts multiple first level triggers, freezes the corresponding analog data and stores their addresses in an external FIFO. The triggered data can then be read out at leisure whilst simultaneously sampling and storing new triggered events. A first level trigger latency of up to 2 μs is accepted at the maximum LHC clock frequency of 66 MHz. The chip shows an overall gain of 48.2 mV/25000 e − . The mean channel noise is 4.5 mV and the pedestal variation from cell to cell within one channel is 1.9 mV. The total dynamic range has been measured at 4.6 V giving a resolution of 11 bits (0.05%) for the memory itself.