A Feed-Forward Control Based Method to Reduce the Settling Time of Phase-Locked Loops for Frequency Ramp Synthesis

Phase-locked loops (PPLs) are used as ultra-wideband and precise frequency synthesizers for frequency modulated continuous wave signals. Within the settling time the output frequency is not the desired multiple of the input frequency. In case of frequency ramps, the settling time reduces the usable bandwidth of the system or the maximal possible measuring rate. To reduce the settling time we present a feed-forward control (FFC) based method, which adapts the modulation of either the reference frequency or the division ratio of the frequency divider. Two noise-optimized microwave PLLs are optimized using the FFC based method. Simulation and measurement results are compared with each other and demonstrate the performance of the method. For an X-band PLL, the settling time is reduced by a factor of 15.44 to 306 ns, and for a V-band PLL by a factor of 2.3 to 228 ns.