Enhancing the design and performance of a gate-all-around (GAA) charge plasma nanowire field-effect transistor with the help of the negative-capacitance technique

A gate-all-around charge plasma nanowire field-effect transistor (GAA CP NW FET) device using the negative-capacitance technique is introduced, termed the GAA CP NW negative-capacitance (NC) FET. In the face of bottleneck issues in nanoscale devices such as rising power dissipation, new techniques must be introduced into FET structures to overcome their major limitations. Negative capacitance is an efficient effect that can be incorporated into a device to enhance its performance for low-power applications and help to reduce the operating voltage. The Landau–Khalatnikov equation can be applied in such cases to obtain the effective bias. To determine the effects of negative capacitance, lead zirconate titanate (PZT) ferroelectric material, a ceramic material with perovskite properties, is adopted as a gate insulator. This approach diminishes the supply voltage and reduces the power dissipation in the device. Excluding their polarization properties, ferroelectric materials are similar to dielectric materials, and PZT offers abundant polarization with improved reliability and a higher dielectric capacitance. Without proper tuning of the thickness of the PZT material, hysteresis behavior mat occur. Hence, the thickness of the PZT material (tFE) is an essential parameter to optimize the device performance and achieve a reduced threshold voltage for the GAA CP NW NC-FET device proposed herein. Furthermore, varying the thickness of the PZT ferroelectric material can also enhance the performance. When using the highest values of tFE, improved outcomes with an analogously lower operating voltage are observed. The effects of varying tFE on the performance characteristics of the device including the drain current, transconductance, polarized charge, etc. are also interpreted herein.