A Fast Transient Flip Voltage Follower Based Low Dropout Regulator with AC-Coupled Pseudo Tri-Loop Technique Without Using Any Output Capacitor

This paper presents a fast transient low-dropout regulator (LDO) without using any output capacitor for system-on-chip (SoC) powering. Conventional LDO needs a pF to nF level output capacitor for transient voltage drop suppression and encounters stability issue in light load condition. The proposed tri-loop architecture includes a flip-voltage-follower (FVF) stage, an ac-coupled capacitor, and an error amplifier, which resolves the stability issue at different load condition without any output capacitor. The ac-coupled capacitor which forms an ac-coupled loop shortens the response time. The error amplifier (EA) regulates output voltage accurately with high DC gain. The proposed LDO is implemented into an integrated circuit (IC) using 0.18um CMOS process. The whole chip area is 0.398mm2, and the LDO only occupies 0.094mm2. The full transistor-level simulation results demonstrate that undershoot and overshoot voltage are only 270mV and 272mV respectively for load transient of 1-20mA within slew rate of 20mA/100ps. The FVF-based LDO with the proposed technique achieves a response time of 0.225ns, which reaches figure-of-merit (FOM) of 0.388ps.