F p 2 arithmetic acceleration based on modified Barrett modular multiplication algorithm

The quadratic extension field F p 2 is the underlying field in pairing, and speeding up the F p 2 arithmetic will benefit the overall pairing computation largely. This paper we proposed a modified Barrett modular multiplication algorithm and devise an architecture to perform the operation in the form of “AB+ηCD mod M”. In our design, the η is a 5-bit two's complement. The proposed Barrett modular multiplier can implement the fundamental operations of F p 2 multiplication efficiently. The advantages of our design are that the proposed hardware circuit can adapt different parameters of pairing flexibly, and each final result is reduced under modulus M as well, which will shorten the width of the operands and decrease the overhead of the memory access bandwidth. The proposed architecture is synthesized under SMIC 65nm CMOS technology. And the results show that the max work frequency is 709MHz (1.2V) and the design requires 226kGates. It can compute F p 2 multiplication (254 bits) in 0.07us.