Simplified AFDX (full-duplex switched Ethernet) redundancy receiving system and method for processing message by same

The invention discloses a simplified AFDX (full-duplex switched Ethernet) redundancy receiving system. The system comprises physical-layer transceivers, an FPGA (field programmable gate array) module and a CPU (central processing unit) module, wherein the FPGA module comprises at least one circuit consisting of message receiving modules and CPU read-write ports which are connected together; the CPU module comprises message detection modules and a redundancy check module; the number of the physical-layer transceivers and the number of the message detection modules are matched with the number of circuits in the FPGA module; and the physical-layer transceivers, the message receiving modules, the CPU read-write ports and the message detection modules are sequentially connected together, and all the message detection modules are connected with the redundancy check module. After the redundancy receiving system is improved, a module performing redundancy processing in the FPGA module in the prior art is set into the CPU module, so that the working flexibility of the FPGA is improved, and the logic design workload of the FPGA module is reduced.