Benchmarking of FinFET, Nanosheet and Nanowire FET Architectures for Future Technology Nodes

Nanosheet (NS) and nanowire (NW) FET architectures scaled to a gate length ( $L_{\textbf {G}}$ ) of 16 nm and below are benchmarked against equivalent FinFETs. The device performance is predicted using a 3D finite element drift-diffusion/Monte Carlo simulation toolbox with integrated 2D Schrodinger equation based quantum corrections. The NS FET is a viable replacement for the FinFET in high performance (HP) applications when scaled down to $L_{\textbf {G}}$ of 16 nm offering a larger on-current ( $I_{\textbf {ON}}$ ) and slightly better sub-threshold characteristics. Below $\text{L}_{\textbf {G}}$ of 16 nm, the NW FET becomes the most promising architecture offering an almost ideal sub-threshold swing, the smallest off-current ( $I_{\textbf {OFF}}$ ), and the largest $I_{\textbf {ON}}/I_{\textbf {OFF}}$ ratio out of the three architectures. However, the NW FET suffers from early $I_{\textrm {ON}}$ saturation with the increasing gate bias that can be tackled by minimizing interface roughness and/or by optimisation of a doping profile in the device body.