Implementation of chip-level EMC strategies in 0.18 μm CMOS technology

Two on-chip electromagnetic compatibility (EMC) solutions realized in the standard 0.18 μm CMOS technology are proposed. A slew rate controller for electromagnetic interference (EMI) reduction is demonstrated by increasing the rise and fall time of signal to lower the harmonic energy on FFT spectrum. Besides, a MOS plus MOM decoupling capacitor for both EMI and electromagnetic susceptibility (EMS) issues is proposed to provide a 17.6 % added capacitance than the conventional decoupling capacitors under the same area. The experiment results prove that the proposed EMC strategies are effective and can be utilized in the chip design with low design complexity.