Electrical backplane equalization using programmable analog zeros and folded active inductors

A low power small area electrical backplane equalizer using programmable analog zeros and folded active inductors is presented in this paper. The equalizer circuit was implemented in a 1.0-V TSMC 90nm CMOS process. With one zero stage, the equalizer occupies only 0.015mm 2 chip area and dissipates 8mW power. At 3.125Gb/s data rate, lab measurement shows that the equalizer provides 6.5dB gain boost at the baud-rate frequency. Without the use of any transmitter equalization, the analog equalizer opens the received eye which is almost closed and demonstrates error-free transmissions for a PRBS-31 data pattern over a 34 inches FR4 backplane