Via Design Optimization for High Speed Differential Interconnects on Circuit Boards

The unprecedented demand for high bandwidth applications boosts the data rates of major high speed differential interconnect protocols such as PCIe and Thunderbolt/USB. Transmission lines and via transitions form most of the interconnect path between a transmitter and a receiver. To get maximum performance of the system at high signaling rates, the impedance of the interconnect path has to be as uniform as possible to cause minimal signal reflections. While the impedance of transmission lines can be easily controlled, the impedance of vias are much harder to control. In this paper, we use time-domain impedance waveforms in conjunction with channel simulations to optimize the impedance profiles of 3 types of differential vias: through-hole vias, blind vias and buried vias. We do this by varying the via diameter, pad diameter, antipad diameter and via pitch (center-to-center distance). We then show a quick method to optimize the vias for faster turnaround time, depending on whether the via impedance is too capacitive or too inductive. The board designer can use the quick method to try to achieve approximately the impedance profiles we show.