A high speed sampler for sub-sampling IR-UWB receiver

A high speed sampler for a sub-sampling impulse radio UWB receiver is presented. In this design, the sampler uses a time-interleaved topology with a single track and hold circuit, full custom clock generator, and offset cancelled comparator. These three main blocks are also discussed and analyzed. The circuit was fabricated in 0.13 μm CMOS technology. Measurement results indicate that the sampler achieves a maximum 3 GS/s sampling rate. The power consumption of the sampler is 27 mW under a supply voltage of 1.2 V. The total chip area including pads is 1.4 × 0.97 mm2.