A monitor generation method for formal monitor‐based verification considering input constraints

Various kinds of methods have been proposed for hardware module interface verification. We focus on monitor-based formal verification. In our approach, to verify interface specifications more comprehensively, we describe specifications of a module interface in a specification language based on regular expressions, and then behavioral models are constructed. Next, a monitor circuit is generated. This method prevents monitor circuits from involving errors because of automated monitor generation. Usually, input constraints must also be given for a design, when each module is verified one by one, because undesirable input patterns may be provided. Instead of giving input constraints, we propose a method of monitor generation including input constraints. Input constraints are extracted from specification of interfaces. Therefore, verification of individual modules becomes less difficult. We show an experimental result on formal verification of circuits compliant to the AMBA AHB bus protocol. © 2007 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 90(12): 19–26, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjc.20360