A 0.18- $\mu$ m LDMOS With Excellent Ronsp and Uniformity by Optimized Manufacture Process

In this paper, a $0.18~{\mu }\text{m}$ n-type lateral DMOS (LDMOS) is researched. By optimized manufacture process and device structures, ultra-low specific on resistance ( ${R} _{\mathrm {onsp}}$ ) is achieved. Pbody and n-type drift region are all full self-aligned implantation (FSAI). For different structures, the uniformities of the dc parameters affected by the process variation are researched. Experimental results show that: by optimizing manufacture process and device structures, the FSAI nLDMOS has competitive ${R} _{\mathrm {onsp}}$ compared with other technologies. For Breakdown voltage equals to 42 V and 52 V, the ${R} _{\mathrm {onsp}}$ are 18.7 $\text{m}{\Omega \bullet }$ mm 2 and 30 $\text{m} {\Omega \bullet }$ mm 2 , respectively. For FSAI-nLDMOS, both simulation and experiment demonstrated that the shift of the dc parameters generated by the process variation is superior to the other technologies. Moreover, only one n-type drift region with filed oxide is used. The device is fabricated in bulk-silicon without epitaxy. These leads to the low cost of the fabrication.