Improving functional verification of embedded systems using hierarchical composition and set theory

During functional verification, complex interactions between multiple modules that compose a digital circuit design can reveal hard-to-find bugs. Functional coverage specifications must be precise to assure these interactions occur during the simulation. We are proposing a technique for improving the functional verification specification of individual modules, preserving the occurrence of these interactions scenarios in the composition phase. We obtain these new specifications in a deductive way, by means of set theory. Using experimental results, we show how our work can contribute to error detection and save functional verification time.