Modified instruction pipeline for obfuscated multi threaded computer programs

Obfuscating multi-threaded computer programs is carried out via instruction pipeline 16 in a computer processor by streaming first instructions 24 of a first thread into the pipeline, the instructions entering the pipeline at fetch stage 28, detecting a stall signal indicative of stall condition, and, responsively to the signal, injecting 40 second instructions of a second thread 42. The injected second instructions enter the pipeline at an injection stage downstream from the fetch stage up to and including the register stage 32. The injection stage can be the register stage 32. The stall condition exists at one stage upstream from the injection stage, for example decode stage 30. Additional signal, such as the absence of a stall in the injection stage, can also be detected. First and second instructions can be fetched using first/second buses 22 and 44. Second instructions to be fetched can be selected via an ancillary program counter 48. A stall signal can be generated irrespective of a stall condition for a time sufficient to executing the second thread. First and second threads are multiplexed (54) in the register stage of the pipeline. The second thread has a flow of control unaffected by processing injected second instructions.