Dependence of ${V}_{\text {TH}}$ Stability on Gate-Bias Under Reverse-Bias Stress in E-mode GaN MIS-FET

In this letter, we investigated the threshold voltage ${V}_{\text {TH}}$ stability under reverse-bias step-stress in the E-mode LPCVD-SiN x /PECVD-SiN x /GaN MIS-FET. Under the OFF-state reverse-bias stress with the same net gate-to-drain voltage ( ${V}_{\text {GD}}$ ), the ${V}_{\text {TH}}$ shift shows an obvious dependence on the negative gate bias. With a ${V}_{\text {GS}}$ of 0 V, the ${V}_{\text {TH}}$ shift is small and recoverable, while the ${V}_{\text {TH}}$ shifts are substantially larger with more negative gate bias ( ${V}_{\text {GS}}=-20$ V). This larger ${V}_{\text {TH}}$ shifts caused by the negative ${V}_{\text {GS}}$ can be explained with a hole-induced degradation model. An important indication revealed by this model is that negative gate bias should be well confined in high-power switching applications of GaN E-mode MIS-FET for a stable ${V}_{\text {TH}}$ .