An Optimized Solution for Cross-Domain System Bus Transaction Processing

Since multi-core processor and System-On-Chip (SOC) have developed fast in recent years, the interconnection bus becomes a key factor to system performance. Recently, it is reported that for most desktop and embedded systems, bus bandwidth has not been fully exploited, and the data transfer efficiency is low. In this paper, we show that the frequent cross-domain bus transaction is the main bottleneck of I/O performance promotion. Then based on a Hyper Transport (HT) 3.0 bus controller design, we propose an optimization scheme which includes a pipelined design methodology for cross-domain bus transaction and asynchronous FIFO designs using Globally Ratiochronous Locally Synchronous (GRLS) technology. The experiment shows that our solution increases the HT bus read and write bandwidths about 34.8% and 13.5% respectively, and it reduces the latency about 40%. Although our solution is based on well known system buses technologies - AMBA AXI and HT bus technologies, it can be easily implemented in systems with other bus technologies.