Enabling Solutions for 28 nm CMOS Advanced Junction Formation

Controlling short channel effects for further scaled CMOS is required to take full advantage of the introduction of high K/metal gate or stress induced carrier mobility enhancement. Ultra‐Shallow junction formation is necessary to minimize the short channel effects. In this paper, we will discuss the challenges for 28 nm Ultra‐Shallow Junction formations in terms of figure of merits of Rs/Xj and junction leakage. We will demonstrate that by adopting and integrating Carborane (CBH, C2B10H12) molecular implant and Phosphorus along with co‐implantation and PTC II (VSEA Process Temperature Control) technology, sub‐32 nm pLDD and nLDD junction targets can be timely achieved using traditional anneals. Those damage engineering solutions can be readily implemented on state‐of‐the‐art 28 nm device manufacturing.