The new approach of programmable pseudo fractional-N clock generator for GHz operation with 50% duty cycle

Because SOC (system-on-a-chip) needs multiple clocks and mostly with 50% duty cycle in same chip, in this paper, we propose a new approach of programmable pseudo fractional-N clock generator to reach a simple solution. We use multiphase outputs of voltage-controlled oscillator (VCO) in a phase-locked loop (PLL), to generate the needed frequencies with 50% duty cycle. Moreover, a control logic is also built in the structure to make multiple frequency outputs programmable. The circuits are processed in a standard 0.13/spl mu/m CMOS technology, and work with a supply voltage of 1.2V.