Investigation of Gate Etch Damage at Metal/High- $k$ Gate Dielectric Stack Through Random Telegraph Noise in Gate Edge Direct Tunneling Current

Plasma damage on a high-k/SiO 2 dielectric at a gate edge during a dry etch process is investigated. The damage was observed to generate slow oxide traps, causing a random telegraph noise (RTN) in a gate edge direct tunneling current. Through the analysis of the RTN, the distribution of the oxide traps in the high-k/SiO 2 dielectric was obtained, and the plasma-damage-induced oxide traps were found to be distributed over a wide area of the high-k/SiO 2 sidewall at the gate edge region.