Circuit arrangement for voltage stabilization

The invention relates to a circuit arrangement for voltage stabilisation, arranged between two signal lines, each with a signal, whereby an interference signal is superimposed on at least one signal, comprising an amplifier circuit, which records a signal derived from the interference signal as the difference from a reference signal, amplifies the above and generates a counter-phase signal to the above. Said arrangement further comprises a matching circuit in series with the amplifier circuit, which generates a compensation signal from the counter-phase signal and superimposes the same on the signal, superimposed with the interference potential.