Electronic alignment for proximity communication

This work presents an electronic alignment mechanism for capacitively-coupled proximity communication. On an experimental chip, position offsets of up to +/-100/spl mu/m are electrically corrected to within 6.25/spl mu/m. A 0.35/spl mu/m experimental CMOS chip communicates at 1.35Gb/s with a BER /spl les/10/sup -10/.