Evaluation of Standard Cell Architecture in 12LP FinFET Technology

In FinFET technology, layout and process design of experiments (DOEs) are established to assess silicon to spice correlation of alternative standard cell architecture such as double diffusion break (DDB) v/s single diffusion break (SDB). Also impact due to variation in middle of line (MOL) is evaluated by comparing it to a reference design. Subsequent process improvements are measured based on the established DOE’s to ascertain DDB and SDB architecture have improved.