Electrical performance of 130 nm PD-SOI MOSFET with diamond layout

Abstract Some special effects of SOI devices with diamond layout are analyzed in this paper based on the silicon data from 130 nm PD-SOI T-gate MOSFET. LCE and PAMDLE induced current gain dependence on geometry parameters of devices with fixed gate area and fixed smallest channel lengths are presented. BVDS of different diamond devices are studied and discussed and a specified geometry has been found with better BVDS performance. For the special shape of channel region, the hot-carrier effect induced body current is collected in the experiment and the mechanism of body current increasing has been analyzed theoretically.