Low Power 6-b CMOS Folding-Interpolating A/D Converter

An 6-bit CMOS folding-interpolating analog-todigital converter (ADC) is presented. The operation of current steering folding amplifier and current-mode interpolation performance are described. Simulated in a 0.35 ㎛ 1p4m CMOS process, careful circuit design leads to a high-speed (250 Ms/s) and low power (18 ㎽ in 3.3 V supply voltage) ADC. Simlation results also show both integral and differential non-linearity (INL, DNL) are within ±0.2 lsb and signal-to-noise-and-distortion ratio (SNDR) of 37.1 ㏈ at 250 Mhz/s sampling rate.