A novel approach for ESD-immunity analysis using channel transfer impedance on the power delivery network of a large-scale integration chip

In this work, we proposed a novel approach for electrostatic discharge (ESD) noise stress analysis using transfer impedance analysis in a platform for a large-scale integration chip. In the electronic industry an ESD test is widely taken to evaluate the noise immunity of a designed electronic device. In this ESD test, critical hardware damage or functional problems may occur due to temporary electrical disturbances produced by applying an external electrical shock. By manipulating the transfer-impedance difference from a noise-induced point to power/ground points of an IC, the influence of an induced ESD noise that could significantly affect the IC's performance was analyzed. The ESD noise stress affects supply voltage to become unstable in a power delivery network (PDN) and adversely affects analog/digital circuit operations during data processing. The impedance differences in the PDN produces supply voltage instability in a designed chip. Thus, by analyzing the transfer impedance from the PCB to the power nets of a time-controller IC, the variation of supply voltage due to external ESD noise can be estimated. In order to separate noise-to-power and noise-to-ground paths on a PCB, an additional ground layer, which exists only in simulation, was used for estimating temporal voltage fluctuation due to impedance imbalance between the noise-to-power and the noise-to-ground paths. In comparison, the proposed approach was demonstrated to agree with the measurement up to 500 MHz. This estimation result indicated that the simulation approach on ESD noise immunity using transfer impedance is useful to predict the influence of electrical stress to a designed IC on a PCB. The estimation approach on ESD noise impact is expected to be applicable for the PDN design of a PCB/IC to improve its ESD noise immunity prior to its implementation.