A memory rename table to reduce energy and improve performance

A memory rename table for improved performance, reduced complexity, and reduced energy consumption is proposed and evaluated. It gives an average 8.7% speedup and 7.9% reduction in core and cache energy. The evaluation employs a simulation model for an out-of-order core, similar to the ARM Cortex A15, and McPAT for energy measurements. The improvements are the result of filtering nearly half (45.4%) of memory accesses before they go to cache. Complexity is reduced by replacement of a load store queue with a scalable renaming system. The changes are transparent to the ISA.