A 50 MHz 24 b floating-point DSP

A 24-bit floating-point digital signal processor (DSP) has been developed primarily for speech processing and communication applications. The chip uses 1.0- mu m double-metal CMOS with tungsten silicide technology. The instruction set is upward compatible with an 18-bit DSP. Novel circuit design techniques allowing 40-ns machine cycle time at 50-MHz clock and less than 600-mW power dissipation are described. A built-in self-test is prepared using on-chip IROM and the two 24-bit linear feedback shift registers which are included in I/O registers such as the data register, the serial input registers, and the serial output registers. The DSP design features are summarized. >