Dream Chip Project at ASET

Chapter 9 introduces the results of Japanese national research and development (R&D) initiative of 3D integration technology using through-silicon via (TSV) over the 5-year period from 2008 to 2012. Association of Super-Advanced Electronics Technologies (ASET) conducted the “Development on Functionally Innovative 3D-Integrated Circuit (Dream Chip) Technology Project,” and it was managed by the NEDO organization. The development subjects consisted of thermal management/chip-stacking technology, thin wafer technology, and 3D integration technology, ultrawide bus 3D-SiP, mixed signal (digital -analog) 3D, and heterogeneous 3D technology.